Manufacture of semiconductors has become increasingly complex as the device densities increase. Such high density circuits typically require closely spaced metal interconnect lines and multiple layers of insulating material, such as oxides, formed atop and between the interconnect lines. Surface planarity of the semiconductor wafer or substrate degrades as the layers are deposited. Generally, the surface of a layer will have a topography that conforms to the sublayer, and as the number of layers increase the non-planarity of the surface becomes more pronounced.
To address the problem, chemical mechanical polishing (CMP) processes are employed. The CMP process removes material from the surface of the wafer to provide a substantially planar surface. More recently, the CMP process is also used to fabricate the interconnecting lines. For example, when depositing copper leads or interconnect lines, a full layer of the metal is deposited on the surface of the wafer having grooves formed in an oxide layer. The metal layer may be deposited by sputtering or vapor deposition or by any other suitable conventional technique. The oxide layer, such as doped or undoped silicon dioxide, is usually formed by chemical vapor deposition (CVD). The metal layer covers the entire surface of the wafer and extends into the grooves. Thereafter, individual leads 16 are defined by removing the metal layer from the surface of the oxide. The CMP process may be used to remove the surface metal leaving the leads in the grooves. The leads are insulated from one another by the intervening oxide layer.
In general, to carry out the CMP process, a chemical mechanical polishing (CMP) machines is used. Many types of CMP machines are used in the semiconductor industry. CMP machines typically employ a rotating polishing platen having a polishing pad thereon, and a smaller diameter rotating wafer carrier which carries the wafer whose surface is to be planarized and/or polished. The surface of the rotating wafer is held or urged against the rotating polishing pad. A slurry is fed to the surface of the polishing pad during polishing of the wafer.
One example of such prior art systems is described in U.S. Pat. No. 5,964,653. The carrier head disclosed by the '653 patent includes a base and a flexible member connected to the base to define first, second, and third chambers. Pressures within the chambers are independently controllable such that biasing force of corresponding portions of the flexible member against the wafer are independently controllable. The carrier head of the '653 patent also includes a flange attachable to a drive shaft and a gimbal pivotally connecting the flange to the base. The gimbal includes an inner race connected to the base, an outer race connected to the flange to define a gap there between, and a plurality of bearings located in the gap.
Because a gimbal is used to align the wafer carrier with the polishing pad in known CMP systems, the frictional loads on the wafer cannot be isolated from the pressure distribution against the wafer during polishing. In particular, the multiple degrees of freedom provided by the gimbal may disadvantageously convert frictional loads, which generally extend parallel to the surface of the wafer, to normal forces extending perpendicular to the surface of the wafer thereby directly affecting the pressure of the wafer against the polishing pad. The coupling of these frictional forces to the wafer effect the pressure distribution across the wafer which is turn adversely effects the uniformity of removal of the material from the surface of the wafer. Accordingly, an improved CMP apparatus and method are needed.